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buran77 2 hours ago [-]
> logic technology can extend for the first time below the 1 nm node, advancing the era of angstrom-level scaling, where dimensions approach the size of individual atoms. While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM’s 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible.
Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.
What they actually deliver is a "nanostack architecture" built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip.
It's an impressive achievement nonetheless but it looks like the industry has a few too many marketers.
adrian_b 59 minutes ago [-]
As it can be seen from the photos, horizontally the features are much bigger than 5 nm.
For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.
The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.
The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer, but that does not matter directly for the circuit density.
The supposed node size refers to horizontal dimensions, not to vertical dimensions.
Vertical dimensions of around 1 nanometer or less could be achieved already many decades ago, because they depend on growth speed and on time, not on lithography, like the horizontal dimensions.
The industry should have stopped decades ago to talk about the "size" but they should have characterized a CMOS process by its density, e.g. in logic gates per square mm.
However, an actual concrete number would be disliked by marketing, because they could no longer claim that their "1 nm" process is better than the "2 nm" process of another vendor, if their density is not really better.
gabrielhidasy 32 minutes ago [-]
Just get better marketers to say your 2nm process has more gates per sqmm than your competition 1nm process.
kailden 23 minutes ago [-]
Exactly. WatsonX AI quantum angstroms for e-business.
Legend2440 1 hours ago [-]
It's been decades since published node sizes had any connection to actual feature size. Sadly this is just how it works in the semiconductor industry now.
pseudosavant 2 hours ago [-]
My read on it was that they are trying to imply a transistor density (in a 2D plane sense) that is comparable to a 1nm process? But they achieve that through stacking (3D, not 2D) since the features aren't actually anywhere near 1nm?
makeitdouble 2 hours ago [-]
If they're adding a dimension, the marketing should reflect that.
I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"
y1n0 47 minutes ago [-]
“TeraThread”
roflmaostc 2 hours ago [-]
yeah, where on the pictures is the 0.7nm feature?
The linespacing is around 5nm. Is it the white line which is 0.7nm?
TallGuyShort 1 hours ago [-]
I really can't see where the 0.7nm is coming from. The white line looks like it's just an edge of a feature that is "15 rows of silicon atoms", which by some quick arithmetic on Wolfram Alpha has to be AT LEAST ~1.6nm, and the way the rows of atoms appear to be packed in that image and by the provided scale, it seems to be significantly more. Using the white line as a meaningful measurement seems to me to be more misleading than any other interpretation here.
wmf 1 hours ago [-]
It's the equivalent performance of a 0.7 nm planar transistor. It's not about the feature size.
api 43 minutes ago [-]
Better metrics are transistors/mm^2, performance/watt, and raw performance, since at this point "nm" is fluff and easily game-able.
Different companies measure it differently too. This was a while ago, but I remember reading that Intel 10nm was more or less close to TSMC 7nm. I'm sure this is still true to varying degrees.
formerly_proven 1 hours ago [-]
> Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.
We care about PPA (power, performance, area) and not how large or not-large features actually are. Comparing gate lengths between a 1980s planar transistor and a 2010s 3D FinFET or GAA transistor is obviously nonsense, the relatively aligned node names of the industry actually do make sense as a shortcut here.
colechristensen 1 hours ago [-]
You have to admit it's getting progressively sillier though.
cyanydeez 2 hours ago [-]
On the otherhand, no investor really cares what it's called, they just need to know it's next gen.
2 hours ago [-]
jadar 4 minutes ago [-]
Just to be clear, this doesn't mean that anything on the die actually measures 0.7nm — it means that it's roughly double the density as the previous node generation. At some point the industry decided to keep talking about "nanometers" even though the actual transistor sizes have been decoupled from the node name for years.
monirmamoun 43 minutes ago [-]
Two big problems 1) NOBODY knows what IBM's definition of "sub 1nm" means 2) IBM bullshits so much more than anyone including Intel (remember the "teleportation" ads years ago) that nobody is going to waste time researching what they mean in reality
wmf 13 minutes ago [-]
I know what it means. Something isn't automatically bullshit because it's outside your field of expertise.
alexey-salmin 27 minutes ago [-]
The most surprising part for me is that IBM still somehow owns silicon labs, I was sure it's effectively a consulting company by now
dekhn 10 minutes ago [-]
Most of their fabs were divested to GlobalFoundries, but they still have pretty significant fab capability and capacity- I suspect at least partly to have a us-based chip-making for military ("Trusted Foundry").
turtletontine 14 minutes ago [-]
The labs might not be that different from consulting, the NYT reporting on this notes they run R&D labs so they can license the tech they develop to people who actually make chips.
Barrin92 14 minutes ago [-]
IBM has been the company with the most patent registrations in the US for I think 29 of the last 30 years. They're one of the largest industrial research organizations in the world. They're doing more hard science research than almost anyone else.
victor106 28 minutes ago [-]
Keep hearing that IBM makes these incredible chips but don’t see anyone using IBM chips. What do they do with them?
jjk7 6 minutes ago [-]
usgov
giwook 2 hours ago [-]
How does IBM commercialize this? Do they license this out to fabs?
topspin 1 hours ago [-]
> Do they license this out to fabs?
Broadly speaking yes, this is the business model. IBM has been at this for many years with technology transfers, licensing agreements, support and other arrangements. Rapidus, Samsung, GlobalFoundries, ST, SMIC, AMD, etc. have all used IBM R&D work at various times for various nodes and products.
The cutting edge of semiconductors is a writhing mass of copulating tapeworms, and IBM lives deep inside that ball. For IBM, what this means is that when you buy one of the ASML machines to make products with this process, you'll pay IBM for the knowledge and support to actually get it working, or give them a cut, or something else, TBD, as circumstances warrant.
wmf 2 hours ago [-]
They licensed 2 nm to Rapidus so yes.
drob518 2 hours ago [-]
I’m sure they will license it. It’s better for them if everyone in the industry can innovate on everything around it. All the process tech companies will make it more cost effective, for instance, which helps IBM as well.
WaxProlix 2 hours ago [-]
Sit on a patent and try to scrape earnings from others, maybe? That is, license or litigate.
evanjrowley 2 hours ago [-]
boost sales for their systems division, POWER CPUs, mainframes, maybe Quantum stuff
TallGuyShort 2 hours ago [-]
I always feel like I'm not quite getting quantum stuff no matter how much I read and learn: what does this advancement have to do with quantum computers?
throw0101d 1 hours ago [-]
One of the images has "15 rows of Si atoms".
Is there a limit to how small things can go? A single atom?
Is there a physical/molecular limit to Moore's Law?
vitally3643 1 hours ago [-]
Yes, and we're already there. We've been there for quite a while, in fact.
Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know. Electrons just aren't physical objects at this scale, you can't simply exclude them from any given volume of space. The electron wave function will simply just appear wherever it wants (within the electron probability cloud). The only way to stop it is to make your insulating junction thicker than the probability cloud.
BitwiseFool 37 minutes ago [-]
>"The electron wave function will simply just appear wherever it wants (within the electron probability cloud)."
I don't know which is more ridiculous, the fact that reality works like this, or, that a species of apes was able to figure this out.
Can you make transistors using that technique? Can you smaller?
colechristensen 1 hours ago [-]
I mean, you can't get smaller than an atom, there is some amount of plausibility of using individual atoms as at least the occasional computing element.
Beyond that, engineering a quark-gluon plasma as a processor? I'd watch that Star Trek episode. (we might fantasize about stuff like that but we're roughly monkeys smashing rocks together in a cave vs. building an iPhone sort of gap away from that kind of thing unless somebody has a really good idea)
vitally3643 1 hours ago [-]
You could, in principle, use photons and/or electrons. We got pretty damn close in the vacuum tube era, and photonic computing has been a popular research topic for a while.
You also have quantum computing, which I think can/does use subatomic particles? Not sure about that one
HarHarVeryFunny 9 minutes ago [-]
It depends on the type of quantum computer. In some a physical qubit is a single atom, but then to make it reliable they need to add error correction resulting in logical qubits consisting of at least 100 or so physical qubits.
Another type of quantum computer uses qubits consisting of "quantum circuits" which are actually huge macroscopic constructions (> 1mm).
superjan 24 minutes ago [-]
You can’t make smaller chips features with photonics. Visible light photons have a wavelength between 400 and 800 nm, much larger than current chip features. When you go to higher frequencies they get smaller, but they are really difficult to produce and control.
petcat 2 hours ago [-]
> IBM and its partners conduct this work at a leading semiconductor research facility in Albany, New York, which will soon be home to a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography tool, essential for the future of logic scaling. Developed by ASML, this technology enables ultra‑precise circuit printing, supporting the creation of smaller, more powerful chips.
I'm guessing that this is the technology that is developed by Cymer (ASML subsidiary) in California, correct? Is there competing technology? I know xLight is trying to make some inroads on their own version of this EUV tech. I have not heard about any progress though.
Why doesn't the industry use something like transistor density per cubic cm? This would extend to 3d cases and impossible to fake
zamadatix 41 minutes ago [-]
The industry does use a collection of more practical measurements, like transistor density. Marketing pieces for the news tend to use this kind of jargon precisely because it can be fudged & it sounds like it means something else than it really does to the average person. It's also simple enough to avoid needing to really explain what kinds of numbers are impressive etc, everyone just knows less than 1 nm is tiny and they've heard X nm for decades to compare to at this point.
perching_aix 10 minutes ago [-]
[delayed]
markhahn 30 minutes ago [-]
has anyone found a paper with details?
also, I was expecting to see cfets mentioned.
stackedinserter 51 minutes ago [-]
Since a transistor can't be smaller than a single atom, maybe it's time to start optimizing our software again.
1 hours ago [-]
ginko 2 hours ago [-]
IBM regularly announces silicon breakthroughs like this but I'm not aware of those ever becoming products. Is IBM mainly in the business of licensing their technology to big silicon manufacturers with stuff like this? Is it just marketing for their consulting business?
vessenes 2 hours ago [-]
My understanding is they are largely an IP business. That said this release mentioned an ASML machine on prem, so?
ijidak 2 hours ago [-]
IBM's contributions to computing hardware and software are incalculable.
So many breakthroughs in hard drives, chips, transistor density, and other aspects of computing have come out of their labs.
Great to see them continuing to innovate.
But, yeah, usually they partner and license. Over the years, they've spun off more and more of their hardware businesses.
petra 1 hours ago [-]
It's great that they found a working business model for a pure r&d lab, and with such awesome results.
I believe that IBM makes the chips for their Z Series mainframes. I mean, that's low volume production, but they need small feature size.
nradov 2 hours ago [-]
IBM Z series mainframe Telum CPUs are designed by IBM but manufactured by Samsung. IBM no longer owns any fabs. I assume they have some kind of technology licensing deal.
Per IBM: "IBM Research at Albany [...] includes more than 100,000 square feet of semiconductor fabrication space"
I guess that is technically a R&D fab not a production one, but they definitely have in house fabrication capability
topspin 1 hours ago [-]
It's a lab. It's where ASML brings up the prototype machine and gets it working, with IBM talent working out the problems and getting it ready for commercial operation. They won't make chips at scale there: the facility isn't designed for that part. The thing to understand here is that isn't a simple, clean, comprehensible business arrangement. The Albany facility is highly subsidized by the state. IBM has their hooks deep in the operation and occupation of the site. Such facilities are extraordinary with capabilities that talent that are unique and fabulously expensive. That's why ASML is there, and not just doing it in some village in the Netherlands. It's why when Obama, Biden, Trump or whomever tells ASML to whom they will and won't be selling hardware, ASML listens.
petcat 46 minutes ago [-]
> It's why when Obama, Biden, Trump or whomever tells ASML to whom they will and won't be selling hardware, ASML listens.
My understanding is that ASML's acquisition of Cymer in California (the actual EUV light source technology) in 2014 was only permitted under a strict technology sharing and export agreement with the US government. And that the technology development and production had to remain within the US.
The USA CHIPS Act and NY State have provided $100 billion+ in funding with the expectation that ASML's core R&D and "prototyping" like this will be done in the US in partnership with US companies (like IBM).
applfanboysbgon 2 hours ago [-]
For anyone who needs it, a friendly reminder that CPU nm marketing is a complete fabrication and the physical size of transistors has zero relation to the marketing claims. These are not, in fact, physically sub 1 nm, despite the bombastic claims.
lp4v4n 2 hours ago [-]
>These are not, in fact, physically sub 1 nm, despite the bombastic claims.
Why? What's their real size?
Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.
CAP_NET_ADMIN 1 hours ago [-]
At some point in the transistor scaling, the electrons started leaking across the gate, we've switched from 2D design to 3D structures to prevent that, so the actual physical gate pitch for like the TSMC 3nm is around 45 nm in distance.
Currently thrown around numbers mean the "equivalent performance/density" or something like that.
applfanboysbgon 1 hours ago [-]
They don't describe the exact physical size (that would rather defeat the point of the marketing), but you can see the photographs at the bottom have a scale measured in tens of nm.
wmf 2 hours ago [-]
The marketing nm better represent the density and performance of the transistors than the actual feature size, especially in this case.
micw 2 hours ago [-]
So the title should be corrected. The did not debut sub nm chips at all.
antisthenes 1 hours ago [-]
That ship sailed long ago. I think it was around 32nm-22nm node when the marketing term started diverging from the physical feature size.
mxuribe 2 hours ago [-]
A little bit of a nitpick, but wouldn't that be a picometer instead of angstrom node? Like, isn't a "pico-" the next magnitude smaller than "nano-", or am i wrong?
Otherwise, that chip tech sounds really awesome - at least for the future!
saulpw 2 hours ago [-]
There are 3 orders of magnitude between nano (^-9) and pico (^-12). An Angstrom is ^-10m.
1313ed01 2 hours ago [-]
Useless fact I just learned from Wikipedia: Ångström/Angstrom (in Sweden of course we still use the original spelling) has its own UNICODE symbol, Angstrom sign: Å (U+212B) not to confuse with the Swedish letter Å (U+00C5). Looks slightly different in my browser.
Looks like that's deprecated. From the next sentence:
However, version 5 of the standard already deprecates that code point and has it normalized into the code for the Swedish letter U+00C5 Å `latin capital letter a with ring above`
mxuribe 2 hours ago [-]
Aaahhh, ok, thanks!
applfanboysbgon 2 hours ago [-]
You had the right idea. Angstroms are not an SI unit. The SI units jump by three orders of magnitude at this scale: picometer, nanometer, micrometer, millimeter.
(In the same way that meter jumps three orders of magnitude to kilometer[1], or millions to billions to trillions, etc.)
[1] Technically there are intermediate SI units between meter and km but nobody uses them. There are not intermediate SI units between the tiny ones.
SoftTalker 1 hours ago [-]
Why above 1mm do we go by tens instead of thousands?
We have centimeter (10 mm) then decimeter (100mm) then meter (1000mm). Then we jump to thousand again (kilometer).
floxy 1 hours ago [-]
>We have centimeter (10 mm) then decimeter (100mm)
Does anyone actually use those? I think I would throw up a little in my mouth if I saw either of those on a mechanical drawing.
topspin 1 hours ago [-]
Answer that question and you'll get the whole impetus for logarithmic scales.
applfanboysbgon 1 hours ago [-]
Everyday necessity. The gap between mm and m is too large, there are many things in daily life that are better expressed in cm. SI units must strike a balance between three factors: not having so many denominations nobody can remember them; not having so few denominations that using them adds too much wordiness to daily life (150mm or 0.15m are wordier than 15cm); and a degree of familiarity with the everyday units people used before metric, to smooth the transition and encourage adoption.
Romario77 1 hours ago [-]
Because 1 angstrom equals 10⁻¹⁰ meters and 1 picometer equals 10⁻¹² meters, the relationship is:
Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.
What they actually deliver is a "nanostack architecture" built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip.
It's an impressive achievement nonetheless but it looks like the industry has a few too many marketers.
For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.
The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.
The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer, but that does not matter directly for the circuit density.
The supposed node size refers to horizontal dimensions, not to vertical dimensions.
Vertical dimensions of around 1 nanometer or less could be achieved already many decades ago, because they depend on growth speed and on time, not on lithography, like the horizontal dimensions.
The industry should have stopped decades ago to talk about the "size" but they should have characterized a CMOS process by its density, e.g. in logic gates per square mm.
However, an actual concrete number would be disliked by marketing, because they could no longer claim that their "1 nm" process is better than the "2 nm" process of another vendor, if their density is not really better.
I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"
Different companies measure it differently too. This was a while ago, but I remember reading that Intel 10nm was more or less close to TSMC 7nm. I'm sure this is still true to varying degrees.
We care about PPA (power, performance, area) and not how large or not-large features actually are. Comparing gate lengths between a 1980s planar transistor and a 2010s 3D FinFET or GAA transistor is obviously nonsense, the relatively aligned node names of the industry actually do make sense as a shortcut here.
Broadly speaking yes, this is the business model. IBM has been at this for many years with technology transfers, licensing agreements, support and other arrangements. Rapidus, Samsung, GlobalFoundries, ST, SMIC, AMD, etc. have all used IBM R&D work at various times for various nodes and products.
The cutting edge of semiconductors is a writhing mass of copulating tapeworms, and IBM lives deep inside that ball. For IBM, what this means is that when you buy one of the ASML machines to make products with this process, you'll pay IBM for the knowledge and support to actually get it working, or give them a cut, or something else, TBD, as circumstances warrant.
Is there a limit to how small things can go? A single atom?
Is there a physical/molecular limit to Moore's Law?
Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know. Electrons just aren't physical objects at this scale, you can't simply exclude them from any given volume of space. The electron wave function will simply just appear wherever it wants (within the electron probability cloud). The only way to stop it is to make your insulating junction thicker than the probability cloud.
I don't know which is more ridiculous, the fact that reality works like this, or, that a species of apes was able to figure this out.
https://en.wikipedia.org/wiki/Landauer%27s_principle
Yes, single-atom manipulation has already been demonstrated:
* https://en.wikipedia.org/wiki/IBM_(atoms)
Can you make transistors using that technique? Can you smaller?
Beyond that, engineering a quark-gluon plasma as a processor? I'd watch that Star Trek episode. (we might fantasize about stuff like that but we're roughly monkeys smashing rocks together in a cave vs. building an iPhone sort of gap away from that kind of thing unless somebody has a really good idea)
You also have quantum computing, which I think can/does use subatomic particles? Not sure about that one
Another type of quantum computer uses qubits consisting of "quantum circuits" which are actually huge macroscopic constructions (> 1mm).
I'm guessing that this is the technology that is developed by Cymer (ASML subsidiary) in California, correct? Is there competing technology? I know xLight is trying to make some inroads on their own version of this EUV tech. I have not heard about any progress though.
also, I was expecting to see cfets mentioned.
So many breakthroughs in hard drives, chips, transistor density, and other aspects of computing have come out of their labs.
Great to see them continuing to innovate.
But, yeah, usually they partner and license. Over the years, they've spun off more and more of their hardware businesses.
I wonder why isn't this more common.
https://www.ibm.com/products/z/telum
Per IBM: "IBM Research at Albany [...] includes more than 100,000 square feet of semiconductor fabrication space"
I guess that is technically a R&D fab not a production one, but they definitely have in house fabrication capability
My understanding is that ASML's acquisition of Cymer in California (the actual EUV light source technology) in 2014 was only permitted under a strict technology sharing and export agreement with the US government. And that the technology development and production had to remain within the US.
The USA CHIPS Act and NY State have provided $100 billion+ in funding with the expectation that ASML's core R&D and "prototyping" like this will be done in the US in partnership with US companies (like IBM).
Why? What's their real size?
Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.
Currently thrown around numbers mean the "equivalent performance/density" or something like that.
Otherwise, that chip tech sounds really awesome - at least for the future!
https://en.wikipedia.org/wiki/Angstrom
However, version 5 of the standard already deprecates that code point and has it normalized into the code for the Swedish letter U+00C5 Å `latin capital letter a with ring above`
(In the same way that meter jumps three orders of magnitude to kilometer[1], or millions to billions to trillions, etc.)
[1] Technically there are intermediate SI units between meter and km but nobody uses them. There are not intermediate SI units between the tiny ones.
We have centimeter (10 mm) then decimeter (100mm) then meter (1000mm). Then we jump to thousand again (kilometer).
Does anyone actually use those? I think I would throw up a little in my mouth if I saw either of those on a mechanical drawing.
1 Å = 100 pm. 1 pm = 0.01 Å.
1 angstrom = 0.1 nanometers, 100 picometers
1 nanometer = 10 angstroms, 1000 picometers